1. Field of the Invention
The present invention relates to a semiconductor device and fabrication methods thereof, and in particular relates to a sawing process of semiconductor fabrications.
2. Description of the Related Art
The semiconductor industry continuously strives to reduce the size and cost of integrated circuits. One method for measuring the performance of an integrated circuit uses the maximum clock speed at which the circuit operates reliably, which depends on how fast transistors can be switched and how fast signals can propagate.
One particular problem confronting the semiconductor industry is that, as integrated circuit scaling continues, the performance improvement is limited by the signal delay time attributable to interconnects in the integrated circuit. According to one definition, integrated circuit interconnects are three-dimensional metal lines with submicrometer cross sections surrounded by insulating material. One definition of an interconnect delay is the product of the interconnect resistance (R) and the parasitic capacitance (C) for the interconnect metal to the adjacent layers. Because of the progressive scaling, the parasitic capacitance (C) has significantly increased due to closer routing of wires, and the interconnect resistance (R) has significantly increased due to a continuous reduction of the wire section. As such, it is desirable to lower the interconnect RC time constant by using materials with a low dielectric constant (k).
Low dielectric constant materials generate many issues when used in semiconductor processes. FIG. 1A˜FIG. 1C show an issue associated with low dielectric constant materials during sawing process. In FIG. 1A, a wafer comprises a plurality of dies, separated by scribe line areas 110. FIG. 1B is an enlarged view of FIG. 1A, which shows dies 102, 104, 106 and 108 are separated by scribe line areas 110. The dies comprise seal rings 112 formed of metal for protecting devices in the dies. Referring to FIG. 1C, after finalizing process steps of semiconductor devices of the dies 102, 104, 106 and 108, the wafer 100 are sawed to separate the dies 102, 104, 106 and 108 for further packaging. The sawing path 114 in the scribe line area is shown in FIG. 1C. Due to stress concentration, peeling 118 or chipping 116, however, is likely to occur at comers of the dies 102, 104, 106 and 108. Specifically, when inter metal dielectric layers of the semiconductor devices use low dielectric constant materials, peeling 118 is more like to occur, and furthermore, delamination is also generated.
In FIG. 1D, the wafer 100 further comprises a plurality of test keys 122 disposed in the scribe line areas 110 for monitoring electric characteristics of the semiconductor devices in the dies 102, 104, 106 and 108 in intermediate stages of fabrications thereof. As shown in this figure, crack or peeling 120 is likely to occur at locations neighboring the test keys 122 during sawing. The crack, peeling or delamination 120 sometimes exceeds the seal ring 112, therefore reducing yield of semiconductor devices.